From nyef@softhome.net Mon Nov 10 18:01:02 2003 From: nyef@softhome.net (Nyef) Date: Mon Nov 10 18:01:02 2003 Subject: [LMH]Raven Microcode Questions Message-ID: <20031111025831.GA23630@miyu.paradiesanalytics.com> Hello all. Over the past couple weeks I've been working on figuring out how the Raven (Explorer I) processor interprets it's microcode. I've got some of it figured out, but I have a few questions. I'm figuring that the condition field of the jump instruction selectively disables the main jump action, in favor of the abbrev-jump field action (if specified). My first question is how do the condition and abbrev-jump fields interact on alu and byte instructions? How does the condition field operate on these instructions without the abbrev-jump field? My second question is what is the encoding for where to store the data when using the jump instruction to read I-Memory? I'm sure there are more questions waiting in the wings. Oh well. If someone could shed some light on these subjects it would be much appreciated. --Alastair From stevelisp@grape-krueger.com Tue Nov 18 00:54:00 2003 From: stevelisp@grape-krueger.com (Steve Krueger) Date: Tue Nov 18 00:54:00 2003 Subject: [LMH]Raven Microcode Questions References: <20031111025831.GA23630@miyu.paradiesanalytics.com> Message-ID: <3FB99C36.7020609@sbcglobal.net> Alastair, I'm sorry I've been slow to answer. I can indeed answer almost any question on the Explorer I microcode engine. Nyef wrote: >Hello all. > >Over the past couple weeks I've been working on figuring out how the >Raven (Explorer I) processor interprets it's microcode. I've got some of >it figured out, but I have a few questions. > >I'm figuring that the condition field of the jump instruction >selectively disables the main jump action, in favor of the abbrev-jump >field action (if specified). > You are right. If the condition is true, the jump action specified by R, P and N bits is performed. If false, the jump action of the abbreviated jump field is performed. Only 000 (And-Nop), 110 (And-Popj) and 111 (And-Popj-Xct-Next) are allowed in the abbreviated jump field of a jump or dispatch microinstruction. > >My first question is how do the condition and abbrev-jump fields >interact on alu and byte instructions? How does the condition field >operate on these instructions without the abbrev-jump field? > The abbreviated jump field is conditioned on the condition selected by the condition field. Like: (And-Call-Illop If-Not-Tag-Equal (M-T) M+1 M-T A-R) This does unary arithmetic on M-T while checking that the tag of M-T is equal to the tag of A-R). > >My second question is what is the encoding for where to store the data >when using the jump instruction to read I-Memory? > Ah, that one I'll have to look up. The M-bus source is written to I<31:00>. The A-bus source bits <23:00> are written to I<55:32>. The write sequence must be: (Call-Xct-Next write-target) (Popj-Inhibit-Xct-Next A-Reg1 M-Reg2 WRITE-IRAM) This writes into the I-Ram at write-target with I<55:32> coming from A-Reg1<23:00> and I<31:00> coming from M-Reg2<31:00>. > >I'm sure there are more questions waiting in the wings. Oh well. > >If someone could shed some light on these subjects it would be much >appreciated. > Again, sorry it took me so long. -Steve From stevelisp@grape-krueger.com Tue Nov 18 06:21:02 2003 From: stevelisp@grape-krueger.com (Steve Krueger) Date: Tue Nov 18 06:21:02 2003 Subject: [LMH]Raven Microcode Questions References: <20031111025831.GA23630@miyu.paradiesanalytics.com> Message-ID: <3FB99C4C.1010901@sbcglobal.net> Alastair, I'm sorry I've been slow to answer. I can indeed answer almost any question on the Explorer I microcode engine. Nyef wrote: >Hello all. > >Over the past couple weeks I've been working on figuring out how the >Raven (Explorer I) processor interprets it's microcode. I've got some of >it figured out, but I have a few questions. > >I'm figuring that the condition field of the jump instruction >selectively disables the main jump action, in favor of the abbrev-jump >field action (if specified). > You are right. If the condition is true, the jump action specified by R, P and N bits is performed. If false, the jump action of the abbreviated jump field is performed. Only 000 (And-Nop), 110 (And-Popj) and 111 (And-Popj-Xct-Next) are allowed in the abbreviated jump field of a jump or dispatch microinstruction. > >My first question is how do the condition and abbrev-jump fields >interact on alu and byte instructions? How does the condition field >operate on these instructions without the abbrev-jump field? > The abbreviated jump field is conditioned on the condition selected by the condition field. Like: (And-Call-Illop If-Not-Tag-Equal (M-T) M+1 M-T A-R) This does unary arithmetic on M-T while checking that the tag of M-T is equal to the tag of A-R). > >My second question is what is the encoding for where to store the data >when using the jump instruction to read I-Memory? > Ah, that one I'll have to look up. The M-bus source is written to I<31:00>. The A-bus source bits <23:00> are written to I<55:32>. The write sequence must be: (Call-Xct-Next write-target) (Popj-Inhibit-Xct-Next A-Reg1 M-Reg2 WRITE-IRAM) This writes into the I-Ram at write-target with I<55:32> coming from A-Reg1<23:00> and I<31:00> coming from M-Reg2<31:00>. > >I'm sure there are more questions waiting in the wings. Oh well. > >If someone could shed some light on these subjects it would be much >appreciated. > Again, sorry it took me so long. -Steve From nyef@softhome.net Mon Nov 24 18:13:01 2003 From: nyef@softhome.net (Nyef) Date: Mon Nov 24 18:13:01 2003 Subject: [LMH]Raven Microcode Questions In-Reply-To: <3FB99C4C.1010901@sbcglobal.net> References: <20031111025831.GA23630@miyu.paradiesanalytics.com> <3FB99C4C.1010901@sbcglobal.net> Message-ID: <20031125043023.GA2790@miyu.paradiesanalytics.com> On Mon, Nov 17, 2003 at 10:12:38PM -0600, Steve Krueger wrote: > Alastair, > > I'm sorry I've been slow to answer. That's okay. I'm on vacation right now anyway, and email access is a little bit sporadic (I'm not paying $10/day for internet). This email will probably not be sent until after I return home on Monday evening. At least I'll have the time to work out a few answers myself... > I can indeed answer almost any question on the Explorer I microcode engine. That's good to hear. I've had to make a couple wild guesses so far, and I'd like to get them straightened out. > You are right. If the condition is true, the jump action specified by > R, P and N bits is performed. If false, the jump action of the > abbreviated jump field is performed. Only 000 (And-Nop), 110 (And-Popj) > and 111 (And-Popj-Xct-Next) are allowed in the abbreviated jump field of > a jump or dispatch microinstruction. Basically what I had figured. > >My first question is how do the condition and abbrev-jump fields > >interact on alu and byte instructions? How does the condition field > >operate on these instructions without the abbrev-jump field? > > The abbreviated jump field is conditioned on the condition selected by > the condition field. Like: > > (And-Call-Illop If-Not-Tag-Equal (M-T) M+1 M-T A-R) > > This does unary arithmetic on M-T while checking that the tag of M-T is > equal to the tag of A-R). Okay, now here I have an additional question. From my disassembly of the E1 proms supplied by Al Kossow: L-197 ((M-0) M+M LOAD-Q M-ONES) L-198 ((M-0) M+1 IF-NOT-EQUAL Q-R M-ZEROS AND-SKIP) Now, M-ONES is M-3, and contains the 32-bit 2s-complement value -1. L-197 sets M-0 and Q-R to the value -2, or #xfffffffe. L-198, almost any way I read it, compares either Q-R or Q-R + 1 (either -2 or -1) to 0, and skips. The problem is that it skips a DPB to IMOD-LOW, which runs as follows: L-199 ((M-0 IMOD-LOW) DPB (BYTE-FIELD 10 19) M-1 M-ZEROS) L-200 ((M-0) SETM Q-R) L-201 ((M-0 IMOD-HIGH) DPB (BYTE-FIELD 10 0) M-1 M-ZEROS) L-202 (CALL SELFTEST-ERROR IF-NOT-EQUAL Q-R M-0) Then, because A-1023 doesn't equal #xfffffffe, it ends up failing the CPU selftest. Or, if A-Memory is all initialized to #xfffffffe, fails when it gets down to A-63, which was previously initialized to 63 during the M- Memory tests. Or maybe when it executes this code again with Q-R equal to #xfffffffd (it's a walking-0 memory test for A-Memory and the PDL-Buffer). The best I've been able to come up with so far as a way out of this is to use the ALU output or Output Bus contents as the M-Source for the condition system and to either subtract 1 from or xor with -1 the A-Source when the ALU Carry Input is set. If you can confirm my reasoning or provide an alternate explanation, it would be much appreciated. > >My second question is what is the encoding for where to store the data > >when using the jump instruction to read I-Memory? > > Ah, that one I'll have to look up. > > The write sequence must be: > > (Call-Xct-Next write-target) > (Popj-Inhibit-Xct-Next A-Reg1 M-Reg2 WRITE-IRAM) > > This writes into the I-Ram at write-target with I<55:32> coming from > A-Reg1<23:00> and I<31:00> coming from M-Reg2<31:00>. I actually had writes figured out, I was more concerned about the read sequence, which is: (call-xct-next read-target) (popj ??? READ-IRAM) Or, from a disassembly: L-304 ((M-0 IMOD-LOW) DPB (BYTE-FIELD 14 18) M-1 M-ZEROS) L-305 (ACCESS-I-MEM) L-306 (READ-I-MEM ...???) I had assumed that this form uses the same destination encodings as the ALU and BYTE instructions, making L-306 (READ-I-MEM (M-6)), and that the other word was stored in Q-R, but that assumption broke down once the walking-1 test of I-Memory passed the 23rd bit. Then I realized that it was executing two read operations per I-Memory location, the second for the high half. Q-R obviously isn't touched, and I<31:31> of the second READ-I-MEM instruction was set, which normally indicates an A-target, but the address was in M-Memory space. My current best guess is that the A/M write-through is disabled during I-Memory reads, and that the A/M target switch also selects the high or low part of the I-Memory word. This opens the question of functional destinations, however, although all functional destinations thus far would be nops. > >I'm sure there are more questions waiting in the wings. Oh well. And here are the first few: What does the ALU output bus control Output-Selector-Mirror do? Does ALU output bus control Output-Selector-RightShift-1 shift in a copy of the sign bit, a 0, the low bit of Q-R, or the carry out from the ALU? Is ALU output bus control Output-Selector-R-Bus a read from Q-R or something else? Does writing to Test-Synch do anything useful like clear the low bit of MD to 0? What exactly does the ALU operation EQV do? How does the rotation direction flag affect the mask calculation for BYTE instructions when mask-rotate is enabled? Is the simplest thing to do here to treat it as the normal case, but take the position as (32 - position) mod 32? What happens when a JUMP instruction has both the call and return bits set? ravfmt.lisp says nop and skip, but ravsym.lisp says jump2-xct-next and jump2. Based on the PROM code, I have to assume that ravsym is correct. Is this right? Does anything get written to the microstack in this case? Between the PROM disassemblies and SSDN2 section 2 (the light code table in particular), I find myself believing that the trap addresses given in ravfmt.lisp are twice the value they purport to be. That is, that the power failure trap address is 2, not 4, and so on down the line. Is this, in fact, the case? > >If someone could shed some light on these subjects it would be much > >appreciated. > > Again, sorry it took me so long. Not a problem. > -Steve --Alastair From nyef@softhome.net Mon Nov 10 18:01:02 2003 From: nyef@softhome.net (Nyef) Date: Mon Nov 10 18:01:02 2003 Subject: [LMH]Raven Microcode Questions Message-ID: <20031111025831.GA23630@miyu.paradiesanalytics.com> Hello all. Over the past couple weeks I've been working on figuring out how the Raven (Explorer I) processor interprets it's microcode. I've got some of it figured out, but I have a few questions. I'm figuring that the condition field of the jump instruction selectively disables the main jump action, in favor of the abbrev-jump field action (if specified). My first question is how do the condition and abbrev-jump fields interact on alu and byte instructions? How does the condition field operate on these instructions without the abbrev-jump field? My second question is what is the encoding for where to store the data when using the jump instruction to read I-Memory? I'm sure there are more questions waiting in the wings. Oh well. If someone could shed some light on these subjects it would be much appreciated. --Alastair From stevelisp@grape-krueger.com Tue Nov 18 00:54:00 2003 From: stevelisp@grape-krueger.com (Steve Krueger) Date: Tue Nov 18 00:54:00 2003 Subject: [LMH]Raven Microcode Questions References: <20031111025831.GA23630@miyu.paradiesanalytics.com> Message-ID: <3FB99C36.7020609@sbcglobal.net> Alastair, I'm sorry I've been slow to answer. I can indeed answer almost any question on the Explorer I microcode engine. Nyef wrote: >Hello all. > >Over the past couple weeks I've been working on figuring out how the >Raven (Explorer I) processor interprets it's microcode. I've got some of >it figured out, but I have a few questions. > >I'm figuring that the condition field of the jump instruction >selectively disables the main jump action, in favor of the abbrev-jump >field action (if specified). > You are right. If the condition is true, the jump action specified by R, P and N bits is performed. If false, the jump action of the abbreviated jump field is performed. Only 000 (And-Nop), 110 (And-Popj) and 111 (And-Popj-Xct-Next) are allowed in the abbreviated jump field of a jump or dispatch microinstruction. > >My first question is how do the condition and abbrev-jump fields >interact on alu and byte instructions? How does the condition field >operate on these instructions without the abbrev-jump field? > The abbreviated jump field is conditioned on the condition selected by the condition field. Like: (And-Call-Illop If-Not-Tag-Equal (M-T) M+1 M-T A-R) This does unary arithmetic on M-T while checking that the tag of M-T is equal to the tag of A-R). > >My second question is what is the encoding for where to store the data >when using the jump instruction to read I-Memory? > Ah, that one I'll have to look up. The M-bus source is written to I<31:00>. The A-bus source bits <23:00> are written to I<55:32>. The write sequence must be: (Call-Xct-Next write-target) (Popj-Inhibit-Xct-Next A-Reg1 M-Reg2 WRITE-IRAM) This writes into the I-Ram at write-target with I<55:32> coming from A-Reg1<23:00> and I<31:00> coming from M-Reg2<31:00>. > >I'm sure there are more questions waiting in the wings. Oh well. > >If someone could shed some light on these subjects it would be much >appreciated. > Again, sorry it took me so long. -Steve From stevelisp@grape-krueger.com Tue Nov 18 06:21:02 2003 From: stevelisp@grape-krueger.com (Steve Krueger) Date: Tue Nov 18 06:21:02 2003 Subject: [LMH]Raven Microcode Questions References: <20031111025831.GA23630@miyu.paradiesanalytics.com> Message-ID: <3FB99C4C.1010901@sbcglobal.net> Alastair, I'm sorry I've been slow to answer. I can indeed answer almost any question on the Explorer I microcode engine. Nyef wrote: >Hello all. > >Over the past couple weeks I've been working on figuring out how the >Raven (Explorer I) processor interprets it's microcode. I've got some of >it figured out, but I have a few questions. > >I'm figuring that the condition field of the jump instruction >selectively disables the main jump action, in favor of the abbrev-jump >field action (if specified). > You are right. If the condition is true, the jump action specified by R, P and N bits is performed. If false, the jump action of the abbreviated jump field is performed. Only 000 (And-Nop), 110 (And-Popj) and 111 (And-Popj-Xct-Next) are allowed in the abbreviated jump field of a jump or dispatch microinstruction. > >My first question is how do the condition and abbrev-jump fields >interact on alu and byte instructions? How does the condition field >operate on these instructions without the abbrev-jump field? > The abbreviated jump field is conditioned on the condition selected by the condition field. Like: (And-Call-Illop If-Not-Tag-Equal (M-T) M+1 M-T A-R) This does unary arithmetic on M-T while checking that the tag of M-T is equal to the tag of A-R). > >My second question is what is the encoding for where to store the data >when using the jump instruction to read I-Memory? > Ah, that one I'll have to look up. The M-bus source is written to I<31:00>. The A-bus source bits <23:00> are written to I<55:32>. The write sequence must be: (Call-Xct-Next write-target) (Popj-Inhibit-Xct-Next A-Reg1 M-Reg2 WRITE-IRAM) This writes into the I-Ram at write-target with I<55:32> coming from A-Reg1<23:00> and I<31:00> coming from M-Reg2<31:00>. > >I'm sure there are more questions waiting in the wings. Oh well. > >If someone could shed some light on these subjects it would be much >appreciated. > Again, sorry it took me so long. -Steve From nyef@softhome.net Mon Nov 24 18:13:01 2003 From: nyef@softhome.net (Nyef) Date: Mon Nov 24 18:13:01 2003 Subject: [LMH]Raven Microcode Questions In-Reply-To: <3FB99C4C.1010901@sbcglobal.net> References: <20031111025831.GA23630@miyu.paradiesanalytics.com> <3FB99C4C.1010901@sbcglobal.net> Message-ID: <20031125043023.GA2790@miyu.paradiesanalytics.com> On Mon, Nov 17, 2003 at 10:12:38PM -0600, Steve Krueger wrote: > Alastair, > > I'm sorry I've been slow to answer. That's okay. I'm on vacation right now anyway, and email access is a little bit sporadic (I'm not paying $10/day for internet). This email will probably not be sent until after I return home on Monday evening. At least I'll have the time to work out a few answers myself... > I can indeed answer almost any question on the Explorer I microcode engine. That's good to hear. I've had to make a couple wild guesses so far, and I'd like to get them straightened out. > You are right. If the condition is true, the jump action specified by > R, P and N bits is performed. If false, the jump action of the > abbreviated jump field is performed. Only 000 (And-Nop), 110 (And-Popj) > and 111 (And-Popj-Xct-Next) are allowed in the abbreviated jump field of > a jump or dispatch microinstruction. Basically what I had figured. > >My first question is how do the condition and abbrev-jump fields > >interact on alu and byte instructions? How does the condition field > >operate on these instructions without the abbrev-jump field? > > The abbreviated jump field is conditioned on the condition selected by > the condition field. Like: > > (And-Call-Illop If-Not-Tag-Equal (M-T) M+1 M-T A-R) > > This does unary arithmetic on M-T while checking that the tag of M-T is > equal to the tag of A-R). Okay, now here I have an additional question. From my disassembly of the E1 proms supplied by Al Kossow: L-197 ((M-0) M+M LOAD-Q M-ONES) L-198 ((M-0) M+1 IF-NOT-EQUAL Q-R M-ZEROS AND-SKIP) Now, M-ONES is M-3, and contains the 32-bit 2s-complement value -1. L-197 sets M-0 and Q-R to the value -2, or #xfffffffe. L-198, almost any way I read it, compares either Q-R or Q-R + 1 (either -2 or -1) to 0, and skips. The problem is that it skips a DPB to IMOD-LOW, which runs as follows: L-199 ((M-0 IMOD-LOW) DPB (BYTE-FIELD 10 19) M-1 M-ZEROS) L-200 ((M-0) SETM Q-R) L-201 ((M-0 IMOD-HIGH) DPB (BYTE-FIELD 10 0) M-1 M-ZEROS) L-202 (CALL SELFTEST-ERROR IF-NOT-EQUAL Q-R M-0) Then, because A-1023 doesn't equal #xfffffffe, it ends up failing the CPU selftest. Or, if A-Memory is all initialized to #xfffffffe, fails when it gets down to A-63, which was previously initialized to 63 during the M- Memory tests. Or maybe when it executes this code again with Q-R equal to #xfffffffd (it's a walking-0 memory test for A-Memory and the PDL-Buffer). The best I've been able to come up with so far as a way out of this is to use the ALU output or Output Bus contents as the M-Source for the condition system and to either subtract 1 from or xor with -1 the A-Source when the ALU Carry Input is set. If you can confirm my reasoning or provide an alternate explanation, it would be much appreciated. > >My second question is what is the encoding for where to store the data > >when using the jump instruction to read I-Memory? > > Ah, that one I'll have to look up. > > The write sequence must be: > > (Call-Xct-Next write-target) > (Popj-Inhibit-Xct-Next A-Reg1 M-Reg2 WRITE-IRAM) > > This writes into the I-Ram at write-target with I<55:32> coming from > A-Reg1<23:00> and I<31:00> coming from M-Reg2<31:00>. I actually had writes figured out, I was more concerned about the read sequence, which is: (call-xct-next read-target) (popj ??? READ-IRAM) Or, from a disassembly: L-304 ((M-0 IMOD-LOW) DPB (BYTE-FIELD 14 18) M-1 M-ZEROS) L-305 (ACCESS-I-MEM) L-306 (READ-I-MEM ...???) I had assumed that this form uses the same destination encodings as the ALU and BYTE instructions, making L-306 (READ-I-MEM (M-6)), and that the other word was stored in Q-R, but that assumption broke down once the walking-1 test of I-Memory passed the 23rd bit. Then I realized that it was executing two read operations per I-Memory location, the second for the high half. Q-R obviously isn't touched, and I<31:31> of the second READ-I-MEM instruction was set, which normally indicates an A-target, but the address was in M-Memory space. My current best guess is that the A/M write-through is disabled during I-Memory reads, and that the A/M target switch also selects the high or low part of the I-Memory word. This opens the question of functional destinations, however, although all functional destinations thus far would be nops. > >I'm sure there are more questions waiting in the wings. Oh well. And here are the first few: What does the ALU output bus control Output-Selector-Mirror do? Does ALU output bus control Output-Selector-RightShift-1 shift in a copy of the sign bit, a 0, the low bit of Q-R, or the carry out from the ALU? Is ALU output bus control Output-Selector-R-Bus a read from Q-R or something else? Does writing to Test-Synch do anything useful like clear the low bit of MD to 0? What exactly does the ALU operation EQV do? How does the rotation direction flag affect the mask calculation for BYTE instructions when mask-rotate is enabled? Is the simplest thing to do here to treat it as the normal case, but take the position as (32 - position) mod 32? What happens when a JUMP instruction has both the call and return bits set? ravfmt.lisp says nop and skip, but ravsym.lisp says jump2-xct-next and jump2. Based on the PROM code, I have to assume that ravsym is correct. Is this right? Does anything get written to the microstack in this case? Between the PROM disassemblies and SSDN2 section 2 (the light code table in particular), I find myself believing that the trap addresses given in ravfmt.lisp are twice the value they purport to be. That is, that the power failure trap address is 2, not 4, and so on down the line. Is this, in fact, the case? > >If someone could shed some light on these subjects it would be much > >appreciated. > > Again, sorry it took me so long. Not a problem. > -Steve --Alastair